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Manuais de instruções e guias do utilizador para Hardware Motorola ColdFire MCF5281.
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Motorola ColdFire MCF5281 Manual do Utilizador (766 páginas)


Marca: Motorola | Categoria: Hardware | Tamanho: 8.69 MB |

 

Índice

MCF5282 and MCF5216 ColdFire

1

Microcontroller User’s Manual

1

Chapter 3

6

Freescale Semiconductor vii

7

Chapter 9

10

Clock Module

10

Chapter 10

10

Interrupt Controller Modules

10

Chapter 11

11

Edge Port Module (EPORT)

11

Chapter 12

11

Chip Select Module

11

Chapter 13

12

Chapter 14

12

Signal Descriptions

12

Freescale Semiconductor xiii

13

Chapter 15

14

Chapter 16

15

DMA Controller Module

15

Chapter 17

16

Chapter 18

17

Watchdog Timer Module

17

Chapter 19

17

Chapter 20

18

Chapter 21

19

DMA Timers (DTIM0–DTIM3)

19

Chapter 22

19

Chapter 23

20

UART Modules

20

Chapter 24

21

C Interface

21

Chapter 25

21

Chapter 26

22

General Purpose I/O Module

22

Chapter 27

23

Chapter 28

24

Freescale Semiconductor xxv

25

Chapter 29

26

Reset Controller Module

26

Chapter 30

26

Debug Support

26

Chapter 31

27

Chapter 32

28

Mechanical Data

28

Chapter 33

28

Electrical Characteristics

28

Appendix A

29

Register Memory Map

29

Appendix B

29

Revision History

29

About This Book

31

Conventions

32

Chapter 1

33

Overview

33

1-2 Freescale Semiconductor

34

Freescale Semiconductor 1-3

35

1-4 Freescale Semiconductor

36

Freescale Semiconductor 1-5

37

1-6 Freescale Semiconductor

38

1.1.1 Version 2 ColdFire Core

39

1.1.2 System Control Module

40

1.1.4 Chip Select

41

1.1.5 Power Management

41

1.1.8 SDRAM Controller

42

1.1.9 Test Access Port

42

1.1.10 UART Modules

42

Freescale Semiconductor 1-11

43

1.2 MCF5282-Specific Features

44

Freescale Semiconductor 1-13

45

1-14 Freescale Semiconductor

46

Chapter 2

47

ColdFire Core

47

2-2 Freescale Semiconductor

48

2.2.1 Data Registers (D0–D7)

50

2.2.5 Program Counter (PC)

53

2.3 Functional Description

55

2.3.4 Processor Exceptions

64

2.3.4.5 Privilege Violation

66

2.3.4.9 Debug Interrupt

67

2.3.4.13 Interrupt Exception

68

2.3.4.14 Fault-on-Fault Halt

68

2.3.4.15 Reset Exception

68

2.3.5.1 Timing Assumptions

72

Table 3-1. EMAC Memory Map

81

3.2.2 Mask Register (MASK)

83

Description.”

85

3.3 Functional Description

86

3.3.1.1 Rounding

88

3.3.1.3 MULS/MULU

90

Three-cycle

91

3.3.4 Data Representation

92

3.3.5 MAC Opcodes

92

3-20 Freescale Semiconductor

98

Chapter 4

99

4-2 Freescale Semiconductor

100

Table 4-1. Cache Memory Map

101

4.3 Functional Description

105

4.3.4 Reset

106

. CLNF Bits

107

Chapter 5

109

Static RAM (SRAM)

109

5.3.2 SRAM Initialization

111

5.3.4 Power Management

112

Chapter 6

113

ColdFire Flash Module (CFM)

113

6.2 Block Diagram

114

Figure 6-1. CFM Block Diagram

115

6.3 Memory Map

116

6.3.1 CFM Configuration Field

117

15 9876543210

118

6.3.3 CFM Registers

119

6.3.4 Register Descriptions

120

31 30 29 16

122

6.4 CFM Operation

128

6.4.1 Read Operations

129

6.4.2 Write Operations

129

6-18 Freescale Semiconductor

130

6.4.3.3 Flash Valid Commands

131

6-20 Freescale Semiconductor

132

6.4.4 Stop Mode

133

6.5 Flash Security Operation

134

6.6 Reset

135

6.7 Interrupts

135

Chapter 7

137

Power Management

137

7.2.2 Memory Map

138

7.2.3 Register Descriptions

138

Table 7-3. XLPM_IPL Settings

139

7 6543210

140

7.3 Functional Description

141

7-6 Freescale Semiconductor

142

7.3.2.3 Flash

143

7.3.2.6 Chip Select Module

143

7.3.2.9 I

144

C Module

144

7.3.2.14 I/O Ports

145

7.3.2.15 Reset Controller

145

7.3.2.17 Clock Module

146

7.3.2.18 Edge Port

146

7.3.2.19 Watchdog Timer

146

7.3.2.23 FlexCAN

147

7-12 Freescale Semiconductor

148

7.3.2.25 BDM

149

7.3.2.26 JTAG

149

Freescale Semiconductor 7-15

151

7-16 Freescale Semiconductor

152

Chapter 8

153

System Control Module (SCM)

153

[31:24] [23:16] [15:8] [7:0]

154

15 10 9 8 0

156

765 32 1 0

158

8.5 Internal Bus Arbitration

159

*Not used on

160

MCF5214/16

160

8.5.2 Arbitration Algorithms

161

15 14 13 12 11 8 7 0

162

8.6.1 Overview

163

8.6.2 Features

164

76 432 0

166

Modules Protected

169

8-18 Freescale Semiconductor

170

9.3 Low-power Mode Operation

172

9.4 Block Diagram

172

Freescale Semiconductor 9-3

173

9.5 Signal Descriptions

174

Register Name Access

175

15 14 13 12 11 10 9 8

176

76 5 4 3210

176

9.7 Functional Description

180

9.7.3 System Clock Generation

181

9.7.4 PLL Operation

181

9-12 Freescale Semiconductor

182

9.7.4.5 PLL Lock Detection

183

9-14 Freescale Semiconductor

184

≠ Feedback Count

184

9.7.4.9 Loss of Clock Reset

185

10.2 Memory Map

194

10.3 Register Descriptions

196

10.3.6.1 Interrupt Sources

203

10-18 Freescale Semiconductor

208

Bits 15–8 Bits 7–0 Access

211

765 43210

212

12.3 Chip Select Operation

217

12.4 Chip Select Registers

218

31 1615 9876543210

220

15 14 13 10 9 8 7 6 5 4 3 2 0

222

12-10 Freescale Semiconductor

224

13.3 Bus Characteristics

226

13.4 Data Transfer Operation

226

13.4.1 Bus Cycle Execution

227

Table 13-3. Bus Cycle States

229

13.4.3 Read Cycle

230

13.4.4 Write Cycle

231

13.4.7 Burst Cycles

234

13.5 Misaligned Operands

238

31 24 23 16 15 8 7 0

239

13-16 Freescale Semiconductor

240

14-2 Freescale Semiconductor

242

C Serial data I/O Ye s

254

C Serial clock I/O Ye s

254

14.1.1 Single-Chip Mode

257

14.2 External Signals

258

14.2.1.2 Data Bus (D[31:0])

259

14.2.1.4 Output Enable (OE)

259

14.2.1.7 Read/Write (R/W)

260

14.2.1.9 Transfer Start (TS)

260

Freescale Semiconductor 14-21

261

14-22 Freescale Semiconductor

262

Freescale Semiconductor 14-23

263

14-24 Freescale Semiconductor

264

14.2.8 FlexCAN Signals

265

14.2.9 I

266

C Signals

266

14.2.10 UART Module Signals

266

14.2.12 DMA Timer Signals

267

14-28 Freescale Semiconductor

268

14.2.14 Debug Support Signals

269

14.2.14.6 Test Clock (TCLK)

270

14.2.15 Test Signals

271

14-32 Freescale Semiconductor

272

Table 15-1. SDRAM Commands

275

15 14 13 12 11 10 9 8 0

277

ACTV command 1 2 3 3

278

31 1817 9876543210

280

15.2.3.1 Address Multiplexing

281

15.2.3.3 Interfacing Example

285

15.2.3.4 Burst Page Mode

285

REF ACTV

288

Freescale Semiconductor 15-17

289

Possible

289

15.3 SDRAM Example

290

ACTV timing

292

31 18 17 16

293

151413121110 876543210

293

1514131211109876543210

295

Power-Up Sequence:

296

Precharge Sequence:

296

Refresh Sequence:

296

31 20 19 16

298

15 12 11 8 7 4 3 0

298

16.3 DMA Transfer Overview

300

31 24 23 0

303

76543210

306

16.5.2 Data Transfer Modes

308

16.5.4 Data Transfer

309

16.5.5 Termination

310

17-2 Freescale Semiconductor

312

Internal Bus

312

Crossbar Switch

312

Master Bus

312

17.1.3 Features

313

17.2 Modes of Operation

314

Register

316

0x114C Access: User read-only

332

17.5 Functional Description

335

17-26 Freescale Semiconductor

336

Data Length

337

Table 17-35. MII Mode

342

17.5.7 FEC Frame Transmission

343

17-34 Freescale Semiconductor

344

17.5.8 FEC Frame Reception

345

17-36 Freescale Semiconductor

346

Freescale Semiconductor 17-37

347

17.5.10 Hash Algorithm

348

Eqn. 17-2

349

17.5.13 Collision Managing

352

17.5.15.1 Transmission Errors

353

17.5.15.2 Reception Errors

353

17-44 Freescale Semiconductor

354

18.5.1 Memory Map

356

Bits 15–8 Bits 7–0 Access

357

765 4 3210

358

Register

362

0x15_0000 (PCSR0)

363

0x15_0002 (PMR0)

365

0x15_0004 (PCNTR0)

366

PCSRn[PRE]

367

19-8 Freescale Semiconductor

368

20.2 Block Diagram

370

20.3 Low-Power Mode Operation

371

20.4 Signal Description

371

Bits 7–0 Access

372

7 6543 0

376

7 654321 0

377

7 65432 0

379

20.6 Functional Description

385

20.6.3 Output Compare

386

20.6.4 Pulse Accumulator

386

20.6.5 Event Counter Mode

386

20.7 Reset

389

20.8 Interrupts

389

20.8.4 Timer Overflow (TOF)

390

Freescale Semiconductor 20-23

391

20-24 Freescale Semiconductor

392

21.1.2 Features

394

0x00_0400 (DTMR0)

395

0x00_0402 (DTXMR0)

397

0x00_0403 (DTER0)

398

0x00_0404 (DTRR0)

399

0x00_0408 (DTCR0)

399

0x00_040C (DTCN0)

400

21.3.4 Output Mode

401

21.4.1 Code Example

401

Eqn. 21-1

402

Freescale Semiconductor 21-11

403

21-12 Freescale Semiconductor

404

22.1.2 Overview

406

22.1.3 Features

406

22.1.4 Modes of Operation

406

Table 22-2. QSPI Memory Map

407

15 141312 11 109876543 210

410

22.4 Functional Description

413

22-10 Freescale Semiconductor

414

22.4.1 QSPI RAM

415

22.4.2 Baud Rate Selection

416

22.4.3 Transfer Delays

417

22.4.4 Transfer Length

418

22.4.5 Data Transfer

418

Freescale Semiconductor 22-15

419

22-16 Freescale Semiconductor

420

23.1.2 Features

422

0x00_0200 (UMR10)

425

0x00_0200 (UMR20)

426

0x00_0204 (USR0)

428

0x00_0204 (UCSR0)

429

0x00_0208 (UCR0)

430

0x00_020C (URB0)

432

0x00_020C (UTB0)

432

0x00_0210 (UIPCR0)

432

0x00_0210 (UACR0)

433

0x00_0214 (UISR0)

434

0x00_0218 (UBG10)

435

0x00_021C (UBG20)

435

0x00_0234 (UIP0)

435

0x00_0238 (UOP10)

436

23.4.1.1 Programmable Divider

437

23.4.2.1 Transmitter

438

Freescale Semiconductor 23-19

439

23.4.2.2 Receiver

440

23.4.2.3 FIFO

441

23.4.3 Looping Modes

442

23.4.3.1 Automatic Echo Mode

443

23.4.3.2 Local Loopback Mode

443

23.4.3.3 Remote Loopback Mode

443

23.4.4 Multidrop Mode

444

UMR1n[PM] = 11

445

23.4.5 Bus Operation

446

Table 23-13. UART Interrupts

447

23-28 Freescale Semiconductor

448

Register Bit DMA Request

448

UISRn 1 Receive DMA request

448

UISRn 0 Transmit DMA request

448

Freescale Semiconductor 23-29

449

23-30 Freescale Semiconductor

450

Freescale Semiconductor 23-31

451

23-32 Freescale Semiconductor

452

Freescale Semiconductor 23-33

453

23-34 Freescale Semiconductor

454

24.1.2 Overview

456

24.1.3 Features

456

24.2.1 I

457

C Address Register (I2ADR)

457

24.2.2 I

457

24.2.4 I

459

C Status Register (I2SR)

459

24.2.5 I

460

C Data I/O Register (I2DR)

460

24.3 Functional Description

461

24.3.3 Data Transfer

462

24.3.4 Acknowledge

463

24.3.5 STOP Signal

463

24.3.6 Repeated START

463

Figure 24-10. Repeated START

464

Freescale Semiconductor 24-11

465

24.4.2 Generation of START

466

24.4.4 Generation of STOP

467

24.4.6 Slave Mode

468

24.4.7 Arbitration Lost

468

C Interrupt Routine

469

24-16 Freescale Semiconductor

470

25.2 The CAN System

474

25.3 Message Buffers

474

Message Buffer 3

478

25.4.2 Receive Process

479

25.4.2.1 Self-Received Frames

480

25.4.4 Remote Frames

481

25.4.5 Overload Frames

482

25.4.6 Time Stamp

482

25.4.7 Listen-Only Mode

482

25.4.8 Bit Timing

482

25.4.9 FlexCAN Error Counters

483

x ≤ 127

483

25-14 Freescale Semiconductor

484

25.4.11.1 Debug Mode

485

25-16 Freescale Semiconductor

486

25.5 Programmer’s Model

487

15 14 13 12 11 10 9 8

488

765 32 0

492

25.5.7 Rx Mask Registers

493

RX15MASK)

494

31 21 20 19 18 17 16

495

26-2 Freescale Semiconductor

502

Freescale Semiconductor 26-3

503

26.1.1 Overview

504

26.1.2 Features

504

26.1.3 Modes of Operation

504

31–24 23–16 15–8 7–0 Access

507

76 5 4 3 2 1 0

513

15 12 11 10 9 8

521

26.4 Functional Description

527

27.3 Block Diagram

530

27.4 Signal Descriptions

530

Bits 31–16 Bits 15–0 Access

531

15 14 11 10 8 7 6 5 4 3 2 0

532

15 109876 5 43 2 1 0

533

27.6 Functional Description

534

27.6.1 Reset Configuration

535

27.6.2 Chip Mode Selection

536

27.6.3 Boot Device Selection

537

27.6.5 Clock Mode Selection

537

27.7 Reset

538

27.8 Interrupts

538

28.2 Block Diagram

540

28.3 Modes of Operation

540

28.4 Signals

541

28-4 Freescale Semiconductor

542

MSB LSB Access

544

15 14 13 12 11 8

548

7 6 5 4 3210

548

Table 28-5. Prescaler f

549

Divide-by Values

549

Divide-by Values (continued)

550

28.6.6 Status Registers

555

28-18 Freescale Semiconductor

556

Table 28-12. Queue Status

559

15 10 9 8

562

28.7 Functional Description

566

28.7.2 External Multiplexing

567

28-30 Freescale Semiconductor

568

28.7.3 Analog Subsystem

569

28-32 Freescale Semiconductor

570

28.7.3.4 Sample Buffer

571

28.7.3.5 Comparator

571

28.7.3.6 Bias

572

28.7.3.8 State Machine

572

28.8.1.1 Queue Priority

572

Freescale Semiconductor 28-35

573

28-36 Freescale Semiconductor

574

Table 28-22. Trigger Events

575

Table 28-23. Status Bits

575

28-38 Freescale Semiconductor

576

Freescale Semiconductor 28-39

577

28-40 Freescale Semiconductor

578

Freescale Semiconductor 28-41

579

28-42 Freescale Semiconductor

580

Freescale Semiconductor 28-43

581

28-44 Freescale Semiconductor

582

28.8.2 Boundary Conditions

583

28.8.3 Scan Modes

584

28.8.4 Disabled Mode

585

28.8.5 Reserved Mode

585

28.8.6 Single-Scan Modes

585

28-48 Freescale Semiconductor

586

28.8.7 Continuous-Scan Modes

587

28-50 Freescale Semiconductor

588

Freescale Semiconductor 28-51

589

28-52 Freescale Semiconductor

590

Freescale Semiconductor 28-53

591

28-54 Freescale Semiconductor

592

28.8.11 Result Word Table

593

28.9.2 Analog Power Signals

594

Freescale Semiconductor 28-57

595

28-58 Freescale Semiconductor

596

Freescale Semiconductor 28-59

597

28-60 Freescale Semiconductor

598

Freescale Semiconductor 28-61

599

28-62 Freescale Semiconductor

600

Eqn. 28-1

601

Eqn. 28-2

601

28-64 Freescale Semiconductor

602

Freescale Semiconductor 28-65

603

28.9.7 Analog Input Pins

604

Filter Capacitor (CF)

605

28.10 Interrupts

606

Freescale Semiconductor 28-69

607

28-70 Freescale Semiconductor

608

29.3 Signals

610

29.4 Memory Map and Registers

610

Bits 7:0 Access

611

29.5 Functional Description

613

29-6 Freescale Semiconductor

614

29.5.2 Reset Control Flow

615

29-8 Freescale Semiconductor

616

29.5.3 Concurrent Resets

617

29.5.3.2 Reset Status Flags

618

30.2 Signal Description

620

30.3 Real-Time Trace Support

620

30.4 Programming Model

623

RDMREG and WDMREG commands

624

151413121110 8765432 0

626

WDMREG command

626

1514131211109 8 76543 0

628

30.5.1 CPU Halt

634

Freescale Semiconductor 30-17

635

30.5.2 BDM Serial Interface

636

30.5.3 BDM Command Set

637

15 1098765432 0

639

30-22 Freescale Semiconductor

640

RAREG/RDREG Command Sequence

641

15 1211 87 432 0

641

RAREG/RDREG Command Format

641

15 12 11 8 7 4 3 2 0

641

WAREG/WDREG Command Format

641

WAREG/WDREG Command Sequence

642

15 12 11 8 7 4 3 1

644

WRITE Command Format

644

WRITE Command Sequence

645

Freescale Semiconductor 30-29

647

15 12 11 8 7 5 4 0

653

30.6 Real-Time Debug Support

655

30.6.1.1 Emulator Mode

656

30.7.1 User Instruction Set

657

30-46 Freescale Semiconductor

664

31.1 Features

666

31.2 Modes of Operation

666

31 28 27 22 21 16

668

15 12 11 10

668

31.5 Functional Description

669

31.5.2 TAP Controller

670

31.5.3 JTAG Instructions

670

31.5.3.2 IDCODE Instruction

671

31.5.3.6 HIGHZ Instruction

672

31.6.1 Restrictions

673

31-10 Freescale Semiconductor

674

32-2 Freescale Semiconductor

676

Freescale Semiconductor 32-3

677

32.2 Ordering Information

683

32-10 Freescale Semiconductor

684

33.2 Thermal Characteristics

686

(continued)

688

Program or Erase

690

± 0.5V, V

693

Figure 33-6. SDRAM Read Cycle

701

Table 33-16. SDRAM Timing

701

Table 33-17. GPIO Timing

702

Figure 33-8. GPIO Timing

703

Table 33-19. I

704

Table 33-20. I

704

Figure 33-10. I

705

C Input/Output Timings

705

Figure 33-15. QSPI Timing

709

Characteristics

709

Symbol Min Max Unit

709

Figure 33-19. TRST Timing

711

Figure 33-20. BKPT Timing

711

A-24 Freescale Semiconductor

736

Appendix C

749




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