2 MC68VZ328 Chip Errata MOTOROLA
5 Real Time Int
Status bits cannot
be masked by
interrupt enable
bits.
Effect:
Unlike other interrupt status registers, each of these status bits is set
when the corresponding event occurs, regardless of its
corresponding interrupt enable bit. If a user uses more than one real
time interrupt or more than one real time clock interrupt, the following
software workaround can be applied.
Workaround:
When an interrupt occurs, service the interrupt only when both its
interrupt enable bit and interrupt status bit are set.
0K85C
2K85C
3K85C
4K85C
5K85C
6K85C
6 The clock
generation module
cannot attain the
maximum PLLCLK
frequency of
77.7216 MHz.
Effect:
(Refer to Figure 4-1 of MC68VZ328 User’s Manual)
The maximum PLLCLK frequency in clock generation module cannot
attain 77.7216 MHz. A minimum of 66.32 MHz is guaranteed. This
erratum will cause the default bootup system frequency to be lower
than 19.4304 MHz in both normal mode and bootstrap mode when a
38.4 kHz crystal is used. The erratum therefore affects the operation
of bootstrap mode because the baud clock generated from system
clock in UART module will not provide the expected 19200 baud for
communication. In short, it is not recommended to run bootstrap
mode if the crystal used is not 32.768 kHz.
Workaround:
No workaround is available. Suggest using 32.768 kHz crystal.
0K85C
2K85C
3K85C
4K85C
5K85C
6K85C
7 Cannot read SPI1
RXFIFO during
data exchanges.
Effect:
User cannot read RXFIFO while SPI1 is receiving data bytes. When
writes to the RXFIFO, from incoming data, and a user read of the
RXFIFO occur simultaneously, the RXFIFO index pointer will not
increment and decrement appropriately. User will see a double byte
received.
Workaround:
Software workaround exists but throughput will be lowered. When
XCH bit deasserts, signalling end of transmission, the user can now
read the RXFIFO.
0K85C
2K85C
8 Cannot write to
SPI1 TXFIFO
during data
exchanges.
Effect:
User cannot write to TXFIFO while SPI1 is transmitting data bytes.
When user writes to the TXFIFO and a read to the TXFIFO, from
data being transmitted, occur simultaneously, the TXFIFO index
pointer will not increment and decrement appropriately. User will see
a double byte transmitted.
Workaround:
Software workaround exists but throughput will be lowered. When
XCH bit deasserts, signalling end of transmission, the user can now
write to the TXFIFO.
0K85C
2K85C
Table 1. Silicon Errata to MC68VZ328 (Continued)
Erratum
Number
Erratum
Description
Workaround
Applies
to Masks
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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