Motorola MVME2400 Series Manual de Serviço descarregar pdf (Página 199)

100

101

Functional Description

http://www.mcg.mot.com/literature 3-13

Note The information in Table 3-4 applies to access timing when

configured for devices with an access time equal to 5 clock

periods.

Note The information in Table 3-5 applies to access timing when

configured for devices with an access time equal to 3 clock

periods.

PowerPC 60x Bus Interface

The SMC has a PowerPC slave interface only. It has no PowerPC master

interface. The slave interface is the mechanism for all accesses to

SDRAM, ROM/Flash, and the internal and external register sets.

Responding to Address Transfers

When the SMC detects an address transfer that it is to respond to, it asserts

AACK_ immediately if there is no uncompleted PowerPC 60x bus data

transfer in process. If there is one in process, then the SMC waits and

Table 3-5. PowerPC 60x Bus to ROM/Flash Access Timing (30ns @ 100MHz)

ACCESS TYPE

CLOCK PERIODS REQUIRED FOR: Total

Clocks

1st Beat 2nd Beat 3rd Beat 4th Beat

Bits

4-Beat Read 34 13 28 7 28 7 28 7 118 34

4-Beat Write N/A N/A

1-Beat Read (1 byte)1313------1313

1-Beat Read (2 to 8

bytes)

3413------3413

1-Beat Write 2121------2121

1 2 ... 194 195 196 197 198 199 200 201 202 203 204 ... 353 354

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