manuais Motorola M68000

Motorola M68000 Manual do Utilizador (92 páginas)

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Índice

MOTOROLA

1

M68000 FAMILY

1

1.1.3 Program Counter

3

Introduction

5

SECTION 2

8

ADDRESSING CAPABILITIES

8

POINTS TO

12

2.2.18 Immediate Data

26

2.6 OTHER DATA STRUCTURES

28

2.6.1 System Stack

28

2.6.2 Queues

29

Addressing Capabilities

30

SECTION 3

31

INSTRUCTION SET SUMMARY

31

3.1.3 Logical Instructions

38

Instruction Set Summary

39

Table 3-19. Conditional Tests

42

3.7 INSTRUCTION DESCRIPTIONS

43

1514131211109876543210

45

1101 REGISTER OPMODE

45

EFFECTIVE ADDRESS

45

MODE REGISTER

45

Add Address

48

(M68000 Family)

49

Add Immediate

50

ADDI Add Immediate ADDI

51

ADDQ Add Quick ADDQ

52

ADDX Add Extended ADDX

54

AND AND Logical AND

56

ANDI AND Immediate ANDI

59

ANDI ANDI

61

Arithmetic Shift ASL, ASR

62

Branch Conditionally Bcc

66

Bcc Branch Conditionally Bcc

67

CMP Compare CMP

68

CMPA Compare Address CMPA

70

CMPI Compare Immediate CMPI

72

CMPM Compare Memory CMPM

74

Integer Instructions

75

JSR Jump to Subroutine JSR

77

Load Effective Address LEA

78

Logical Shift LSL, LSR

79

MOVEA Move Address MOVEA

85

Return from Subroutine RTS

88

Processor Instruction Summary

89

Mnemonic Description

89

(Continued)

90

Table C-2. ASCII Code

91

Motorola M68000 Manual do Utilizador (357 páginas)

Marca: Motorola | Categoria: não | Tamanho: 0.93 MB |

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MOTOROLA

1

M68000 FAMILY

1

TABLE OF CONTENTS

2

LIST OF FIGURES

8

LIST OF FIGURES (Concluded)

9

LIST OF TABLES

10

LIST OF TABLES (Continued)

11

SECTION 5

12

FLOATING POINT INSTRUCTIONS

12

Floating-Point Absolute Value

15

Arc Cosine

19

Floating-Point Add

22

FADD Floating-Point Add FADD

23

FASIN Arc Sine FASIN

25

FATAN Arc Tangent FATAN

28

Floating-Point Compare FCMP

36

FCOS Cosine FCOS

39

FCOSH Hyperbolic Cosine FCOSH

42

Hyperbolic Cosine FCOSH

43

Hyperbolic Cosine FCOSH

44

Decrement, and Branch

45

Floating-Point Divide FDIV

47

FETOXM1 e

54

FGETEXP Get Exponent FGETEXP

57

FGETMAN Get Mantissa FGETMAN

60

FINT Integer Part FINT

63

FLOG10 Log

69

FLOG2 Log

72

FLOGN Log

75

FLOGNP1 Log

78

FMOD Modulo Remainder FMOD

81

⋅), but all

84

< EA > TO REGISTER

86

REGISTER—TO-MEMORY

89

Move Floating-Point FMOVE

91

System Control Register

91

Move Constant ROM FMOVECR

94

Data Registers

100

Control Registers

102

Floating-Point Multiply FMUL

105

Floating-Point Negate FNEG

109

FNOP No Operation FNOP

113

FREM IEEE Remainder FREM

115

FSCALE Scale Exponent FSCALE

118

Floating Point Instructions

121

FSIN Sine FSIN

129

FSINH Hyperbolic Sine FSINH

136

Floating-Point Subtract FSUB

143

FTAN Tangent FTAN

147

Hyperbolic Tangent FTANH

150

FTENTOX 10

153

FTENTOX

153

DESTINATION

158

FTWOTOX 2

161

FTWOTOX

161

SECTION 6

164

ANDI ANDI

165

Invalidate Cache Lines

166

Coprocessor

168

Restore Functions

168

Coprocessor Save Function

170

1514131211109876543210

171

EORI EORI

173

Restore Internal FRESTORE

174

Floating-Point State

174

MOVE MOVE

180

Move Control Register MOVEC

185

Move Address Space MOVES

187

ORI ORI

190

1111000001001COUNT REGISTER

194

0000000000 MC68851 CONDITION

194

16-BIT DISPLACEMENT

194

1111000000

196

EFFECTIVE ADDRESS

196

MODE REGISTER

196

0 0 1 MODE 0 0 MASK FC

196

Flush ATC Entries PFLUSH

198

PFLUSHA PFLUSHA

201

PFLUSH PFLUSH

201

1010000000000000

204

001000R/ W0000 FC

207

SRP, CRP, and TC Registers

211

MMU Status Register

212

TT Registers

213

011000R/W000000000

214

ACx Registers

215

Move PMMU Register PMOVE

216

1111000101

221

PMMU Save Function PSAVE

222

Set on PMMU Condition PScc

225

Test a Logical Address PTEST

226

(MC68030 only)

228

1111000001111 OPMODE

242

Validate a Pointer PVALID

243

Reset External Devices RESET

246

Return from Exception RTE

247

0100111001110010

248

IMMEDIATE DATA

248

SECTION 7

250

CPU32 INSTRUCTIONS

250

Enter Background Mode

253

(CPU32)

253

Low-Power Stop

254

TBLS TBLS

255

TBLU TBLU

260

CPU32 Instructions

265

SECTION 8

266

INSTRUCTION FORMAT SUMMARY

266

Instruction Format Summary

286

X AND BACX REGISTERS

290

TBLU, TBLUN

293

TBLS, TBLSN

293

DATA REGISTER INTERPOLATE

294

FLOGNP1

295

FETOXM1

295

FRESTORE

303

FTRAPcc

303

APPENDIX A

306

PROCESSOR INSTRUCTION SUMMARY

306

Processor Instruction Summary

317

Mnemonic Description

317

(Continued)

318

Data Addressing Modes

321

A.2 MC68020 PROCESSORS

322

(Concluded)

324

Addressing Modes Syntax

325

A.3 MC68030 PROCESSORS

326

A.4 MC68040 PROCESSORS

330

A.6 MC68851 COPROCESSORS

336

APPENDIX B

338

Assignment

339

B.2 EXCEPTION STACK FRAMES

340

Frame, Format $4

342

Format $9

343

15 031 24 23 16

349

VERSION $41

349

(RESERVED)

349

APPENDIX C

352

S-RECORD OUTPUT FORMAT

352

C.2 S-RECORD TYPES

353

C.3 S-RECORD CREATION

354

Table C-2. ASCII Code

356

Motorola M68000 Guia do Utilizador (256 páginas)

Marca: Motorola | Categoria: não | Tamanho: 3.94 MB |

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^UcMttaL P. SizUuijeS i

1

A55EMBLY LANGUAGE

3

PROGRAMMING TOR

3

THE 68000 FAMILY

3

ASSEMBLY LANGUAGE

5

PROGRAMMING FOR

5

TNE 68000 FAMILY

5

To my wife Linda

7

CONTENTS

11

CHAPTER 8: Subroutines 99

12

Contents xl

13

INTRODUCTION

15

Introduction 3

17

NUMBER SYSTEMS

19

Conversions

20

Number Systems 7

21

Hexadecimal

22

2. We can go from binary

23

2 is F0Ai6

23

2 gives us:

23

Representing Negative Values

25

ASCII Character Codes

26

21. binary

29

CHAPTER 2

31

ADDRESS MEMORY

35

User and Supervisor Modes

37

The CPU Registers

38

User Programmer's Model

39

Input/Output

40

ASSEMBLER SOURCE FORMAT

43

The Label Field

44

The Operation Field

46

The Operand Field

46

The Comment Field

47

On Choosing Symbols

48

Constants

48

$1100111001 11001110012

49

Data-Defining Directives

50

Symbol Equates

51

The END Directive

52

Assembler Source Format 39

53

CHAPTER 4

55

Data Movement

55

Getting Started 43

57

Addition and Subtraction

58

Getting 5tarted 45

59

Input and Output

61

The Program Shell

63

Getting Started 51

65

Putting It All Together

67

Getting 5tarted 55

69

#'0',DO

70

19. SUB.L D1,D0

70

CHAPTER 5

71

CONDITION CODE REGISTER

72

The Carry Bit

72

11101001

73

+ 10110111

73

110100000

73

The Overflow Bit

75

The Zero and negative Bits

75

The Extend Bit

76

Com parisons

76

CHP.L DirDO

78

BLE LABEL

78

ADDQ and SUBQ Instructions

80

MOVEQ #100,DO

81

MOVE.L #100,DO

81

BGE LABEL

84

ADDRESSING MODES

85

Register Direct Modes

86

Im mediate Data

86

Absolute Addressing

87

Address Register Indirect

88

Addressing Modes 75

89

Addressing Modes 77

91

Addressing Modes 79

93

Addressing Modes 81

95

Addressing Modes 83

97

Addressing Mode Summary

98

Addressing Modes 87

101

CHAPTER 7

103

Stack Instructions

103

HIGH ADDRESS

104

LOU ADDRESS

104

The 5tach 91

105

LOW ADDRESS

106

Stack Applications

107

The Stack 95

109

Exercises

110

PEA COUNT

111

CHAPTER 8

113

Subroutines 101

115

Passing Param eters

116

Subroutines 103

117

ARG2: DS.L

118

Subroutines 105

119

Subroutines 107

121

ADDA. L # 1 2 ,SP

122

Stack Fram es

123

ID BYTES OF LOCALS

124

Subroutines 111

125

Subroutines 113

127

Subroutines 115

129

CHAPTER 9

131

* Q

139

CHAPTER 10

143

Logical Operations

144

01000100

145

LSL'ASL

147

Bit Manipulation

151

BTSTr BSET, BCLR, BCBG

152

Operand 1

153

Operand 2

153

CHAPTER 11

155

Advanced Arithmetic 143

157

Multiplication and Division

159

11100001

160

Advanced Arithmetic 147

161

Decimal Arithmetic

162

Advanced Arithmetic 149

163

Advanced Arithmetic 151

165

10000 0000

165

Advanced Arithmetic 153

167

EXCEPTION PROCESSING

169

SYSTEM CONTROL

169

OPERATIONS, AND I/O

169

OVFLs DS.B 1

171

OVERFLOW FLAG BYTE

171

Exception Processing

172

TRAP #<vector>

175

ADD.L DO fDl

176

CHK <ea>,Dn

176

Serial I/O

177

I I I I I I I I I I

178

Miscellaneous Instructions

182

8. l e a u s t a c k ,a o

185

C m P T f fl 15

187

MOVE.L (AO)+,MEMLOC

188

Virtual Machines

189

Virtual Address Space

190

Physical Memory

190

Reference Classifications

191

The Vector Base Register

192

RTD and Loop Mode

193

Summ ary

195

9. MOVE CCR,DO

196

PC0, FC1, and FC2

196

The 68010 183

197

CHAPTER 1 4

199

Instruction Caching

200

The 68020 187

201

Additional Addressing Modes

202

The 68020 189

203

MOVE.W #24,DO

203

MOVE.L (0,A0,D0.W*4),D1

203

Instruction Extensions

204

The 68020 191

205

Hew Instructions

207

The 68020 195

209

CAS Dc,Du,<ea>

210

The 68020 197

211

The 68020 201

215

CHAPTER 15

217

Instruction and Data C aches

218

The 68030 205

219

Pipelined Architecture

220

Paged Memory Management

220

requires 10 bits, leaving

221

The 68030 209

223

B-level tables

224

"1 TT1

225

68030 Instructions

225

The 68030 213

227

ASCII CHARACTER CODES

229

PROGRAM SHELLS AND

231

I/O SUBROUTINES

231

! tSt.l dO

232

Appendix B 219

233

Appendix B 221

235

;plain style

236

Appendix B 225

237

; return;

238

Appendix B 227

241

68000-68020

243

0 S 0 S

244

0 S S 0 0 Test Operand

246

00000 Unlink

246

00000 UnPack BCD

246

Appendix C 233

247

236 Index

250

Index 237

251

238 Index

252

Index 239

253

^ U a m a i P

256

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