Motorola MVME2400 Series Manual de Serviço descarregar pdf (Página 87)

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Functional Description

http://www.mcg.mot.com/literature 2-29

Parity:

The PCI Master supports address parity generation, data parity generation,

and data parity error detection.

Cache Support:

The PCI Master does not participate in the PCI caching protocol.

Generating PCI Cycles

There are four basic types of bus cycles that can be generated on the PCI

bus:

❏ Memory and I/O

❏ Configuration

❏ Special Cycle

❏ Interrupt Acknowledge

Generating PCI Memory and I/O Cycles

Each programmable slave may be configured to generate PCI I/O or

memory accesses through the MEM and IOM fields in its XSATTx

If the MEM bit is set, the PHB performs Memory addressing on the PCI

bus. The PHB takes the PPC bus address, applies the offset specified in the

XSOFFx register, and maps the result directly to the PCI bus.

The IBM CHRP specification describes two approaches for handling PCI

I/O addressing: contiguous or spread address modes. When the MEM bit

is cleared, the IOM bit is used to select between these two modes whenever

a PCI I/O cycle is to be performed.

MEM IOM PCI Cycle Type

1xMemory

0 0 Contiguous I/O

0 1 Spread I/O

1 2 ... 82 83 84 85 86 87 88 89 90 91 92 ... 353 354

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Motorola MVME2400 Series Manual de Serviço Página 87

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