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2-8

SHI Port Usage

MOTOROLA

System Overview

DSP Subsystem Code

2.2.2 DSP Run-Time Application

The DSP software is shown in its entirety in

Example 2-2

. As already stated, the DSP

begins execution at

P:$0

. Therefore, a JMP to the main program is executed first. Due to

the simplicity of this DSP application, no X or Y data memory is utilized. Therefore, this

program is already fully loaded and ready to begin execution. However, if the

application did make use of X and/or Y data memory (specifically data variables that

require initial values), then the MCU should complete the boot process by transmitting

the data memory values and the DSP should, of course, receive and store them in the X

data RAM and Y data RAM.

The main program merely initializes peripherals and the core. First, the GPIO port is

programmed so that all of the pins are outputs and sets the initial output data to zero.

Since the DSP boot program required the SHI port to boot internal Program RAM, the

port is already partially initialized for this application. The boot program sets the SHI

port to SPI mode, sets data length to 24-bit data, ensures that HREQ

is asserted when

ready to receive a word, and enables the port. Since this DSP application will respond to

the SHI via interrupt, the Host Receive Interrupt Enable bits (HRIE1–0) of the SHI

Control Status register are set so that an SHI interrupt is generated for “Receive FIFO

Not Empty” and “Receive Overrun” conditions. Next, the core's interrupt handling

system must be configured so that the DSP will respond to the interrupt. First, the SHI is

given an interrupt priority of two by setting the proper bits in the Interrupt Priority

than zero would have sufficed. However, in more complex applications, the priority

structure of the interrupts can be highly significant for optimal DSP system operation.

Next, interrupts are enabled by clearing the interrupt mask in the mode register. Finally,

the main program ends in an infinite loop with background tasks servicing interrupts.

Proper handling of interrupts begins with the interrupt vectors. As stated earlier, the SHI

port will generate interrupts for receive FIFO not empty and receive overrun. These are

two distinctive interrupts. Depending upon the application, the software designer may

decide to handle the situations differently. In this application, they are both handled by

the same routine. A JSR to the SHI_ISR in the interrupt vector table results in the

interrupt service routine being called when either SHI interrupt is generated. The JSR

indicates to the core that a long interrupt will be performed requiring that the interrupt

service routine terminate with an RTI.

The interrupt service routine itself is straightforward. First, the word transmitted from

the MCU to the DSP resides in the HRX register. This word contains a value indicating

which GPIO line should be set high. It is moved into register x0. Notice that a MOVEP

instruction is used to access the peripheral. Next, accumulator A is initialized with the

GPIO port initialization value. Since the GPIO port can only be written to using all 24

bits, the bits responsible for setting the direction of the GPIO pins must be combined

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